1. Field of the Invention
This invention relates to a semiconductor memory device and a controlling method of the semiconductor memory device. More particularly, this invention relates to a nonvolatile semiconductor memory device including MOS transistors, each having a floating gate and a control gate.
2. Description of the Related Art
One known semiconductor memory reading method is to set a bit line to a specific precharge potential and determine the data, depending on whether or not the bit line is discharged as a result of reading the data from a memory cell. This method has also been applied to a flash memory. A flash memory has been disclosed in, for example, Wei-Hua Liu, “A 2-Transistor Source-select (2TS) Flash EEPROM for 1.8-V-Only Application,” Non-Volatile Semiconductor Memory Workshop 4.1, 1997. Hereinafter, this type of flash memory is referred to as a 2Tr flash memory.
Furthermore, in one known data sensing method, a local sense amplifier is combined with a global sense amplifier. In this method, one local sense amplifier is provided for every two or more local bit lines. A global bit line is provided for each local sense amplifier. A global sense amplifier is provided for every two or more global bit lines. The local bit line is precharged by the local sense amplifier.
In the above method, however, not only the local sense amplifier corresponding to the selected global bit line but also the local sense amplifiers corresponding to the unselected global bit lines are activated. Therefore, the unnecessary local bit lines are also precharged. As a result, a large current is supplied to the memory cell array in precharging, which leads to high power consumption.